Do I need to use any special options when running the Xilinx mapping and place and route tools?
The results in the data sheet were obtained with the “-c 1” packfactor option applied during mapping. This causes the Xilinx mapper to pack as much logic as possible into each CLB but usually results in a slightly slower implementation. In most cases the packfactor can be left at the default value. The “-pr b” option can also be used to force the primary I/O registers to be mapped into IOBs if required. During place and route (par) the seed was set to 1 and the effort level set to maximum. The number of delay-based clean up passes was set to 1.
