Does UMC provide any efficient checking methodology of DRC for logic design with embedded memory?

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Does UMC provide any efficient checking methodology of DRC for logic design with embedded memory?

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Layer-marking is one of the approaches to execute the whole chip DRC on an embedded memory cell in a design. It requires a very careful work on the boundary conditions for mask marking and is commonly used by vendors. UMC prefers using memory marker-layers where memory mark layers are well-defined in UMC embedded memory database. In DRC files, 2 sets of the rule checks are applied to logic portion and cell portion respectively and differentiated by the mark layers. With memory marker layers, the violations at memory area are eliminated so that the violations at other area can be reviewed completely.

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