During a system reset the digital channels go high. Is there a way to keep them low?

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During a system reset the digital channels go high. Is there a way to keep them low?

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The digital channels are controlled by an 82C55A peripheral interface chip. This device resorts to high-impedance inputs during a system reset. The GPIO-104 uses 10k pull-up resistors on all 24 digital I/O channels to keep the channels in a known initial state and to allow simple interfacing to external switches, contact closures and open-collector devices. As a consequence, the channels go high while a system is starting up, before the application software has initialized the chip. One solution is to use a ‘strong’ external pull-down resistor on the offending digital channels. During the start-up time the external pull-down and the 10k pull-up will form a simple voltage divider. The pull-down resistor should be chosen so that the voltage divider produces a voltage below the logic ‘1’ threshold of the external device being controlled. After the application software has initialized the 82C55A, the digital channel becomes an output and is actively driven by transistors within the 82C55A.