How big will the HT Mesh expand using the existing ASIC and BL Boss architecture?
The patent, as is typical, is far more general than the implemented ASIC and is therefore virtually boundless depending on number of dimensions and clock speed. The current ASIC implementation scales from 2.5G (single ASIC) to 2.5T (1024 ASICs) with grooming and switching at STS1/STM0 resolution. The Boss 1000 places 4 ASICS on each line card and expands to 16 line cards per chassis and 16 chassis or 256 line cards per system. Obviously there have been some improvements in both chip and backplane technology which could cost reduce and grow this architecture.
