How is EPP mode implemented?
The EPP Mode of operation requires hardware assistance in the form of access to the EPP address port, EPP data port(s), and the ECR register. The ECR register is a control register defined in the “Extended Capabilities Port Protocol and ISA Interface Standard” by Microsoft Corporation. The WARP NINE 1284 driver will switch the interface in EPP Mode by writing 100 in bits 7:5 of the ECR register. For EPP normally a polled mode of operation is provided (with a programmed I/O-based method of data transfer), therefore no IRQ or DMA channel need to be configured. However, optionally EPP Mode could be configured to process an interrupt as indication that the peripheral has data available. If this option is selected, an IRQ needs to be configured.