How many processor cores make up the Nios II processor family?
The Nios II processor is made available as three distinct cores to provide you with maximum design flexibility while balancing system performance needs and logic element (LE) usage. All three cores are included in the Nios II development kits and are supported by the SOPC Builder design tool. The Nios II processor family is made up of these cores: • Nios II/f (fast)–Highest performance, moderate FPGA utilization • Nios II/s (standard)–High performance, low FPGA utilization • Nios II/e (economy)–Modest performance, lowest FPGA utilization What are the benefits of using a soft processor in an FPGA implementation over a hard macro? By implementing a processor as a hardware description language (HDL)-coded intellectual property (IP) core, you get an exact-fit solution because you can choose the peripheral, performance, and processor mix that best suits your system needs. Hard macro implementations are essentially ASICs and do not have the same flexibility; they take so long to deploy that
