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How to use the notplace constrain in Xilinx chip?

chip constrain Xilinx
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How to use the notplace constrain in Xilinx chip?

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Chih-Hsun Lin: 35030: 01/09/18: Increase routing delay in XILINX FPGA editor 35049: 01/09/19: Re: Increase routing delay in XILINX FPGA editor 35103: 01/09/21: Re: Increase routing delay in XILINX FPGA editor Chih-Zong Lin: 21474: 00/03/23: [REQ] download function of Xilinx CPLD 21925

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