How will the Xilinx reuse manual help ASIC designers?
The new “Xilinx Design Reuse Methodology for ASIC and FPGA Designers” is intended for designers who need to be able to target both ASIC and FPGA architectures with the same RTL code. The Xilinx supplement to the Synopsys and Mentor Graphics “Reuse Methodology Manual” provides an overview of FPGA system level features and contains general RTL synthesis coding guidelines that have the most impact on improving system performance. About half of the design reuse issues covered in the “ASIC Designers Programmable Logic Reuse Manual” are targeted at “best coding practices.” This means that while the particular coding technique will optimize the use of logic resources and the performance in an FPGA, it will also do the same for an ASIC design. By enforcing corporate coding and documentation standards, a company will greatly improve the quality of the HDL modules that they are targeting for reuse.
