I debugged my design in ModelSim, but when I upload the .bit file onto the FPGA, it doesn work. What do I do?
Use the logic analyzer to debug the physical signals in your design. It is very common to make some assumption in ModelSim that turns out to be very different in reality, for example signal timings for the I2C bus. Debugging is a step by step process, with ModelSim being step one. 10. I’m not getting any output on the Logic Analyzer. The most common reason for this is you didn’t replace the .ucf file generated by Precision Synthesis with the .ucf file available for download in the MP section of the ECE 412 website. The ucf Precision generates is blank, and in order for the debug outputs to be set up correctly, you must use the one from the website. 11. Certain signals aren’t behaving the way I’m expecting them to on the logic analyzer. There is a good chance those signals are INOUT signals in the design, meaning they can serve either as an input or an output signal, depending on the current state. Since INOUTs get driven by 2 or more sources, we need to avoid the possibility of a short
