Optimization is providing a result with an unusually large Zener clamp loss (PZ). Why?
The Zener clamp loss may become excessive when specifying low-voltage outputs. The problem is more likely when high power levels are specified. In many cases, this is due to an excessive turn’s ratio (NP/NS). To fix this, the designer may be required to reduce reflected output voltage (VOR), thus reducing primary turns and the resulting turns ratio. This will increase peak current and may require a larger PI power device. It is recommended that the designer verify transformer and layout parasitic prior to finalizing his transformer design. This includes transformer leakage inductance (LL) and secondary trace inductance (LSEC). This may be especially true for multiple output power supplies, where the leakage is dependent on the characteristics of all outputs.
The Zener Clamp loss is calculated assuming a leakage inductance (some percent of the primary inductance) and at the peak primary current. In low power applications, these two factors play a large part in determining the overall zener clamp loss. In reality, the clamp loss can be a little lower that what is calculated by the software. It is recommended that the designer verify transformer and layout parasitic prior to finalizing his transformer design. This includes transformer leakage inductance (LL) and secondary trace inductance (LSEC). This may be especially true for multiple output power supplies, where the leakage is dependent on the characteristics of all outputs.
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- Optimization is providing a result with an unusually large Zener clamp loss (PZ). Why?
