Should Dual Rail Go Mainstream in Deep Nanometer Era?
– Electronic Design Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the variability at the cost of additional design efforts. Dual rail solutions appear to be complex, but several area, power, and performance tradeoffs can be made to simplify the design. Read more. Memory Interface IP Sector Heats Up – EE Times Virage Logic and other memory interface IP vendors are now seeing an upswing in business, analysts said. The severe downturn is causing a growing number of OEMs to evaluate or rationalize their internal IP efforts. Read more. AEON® Memory Technology Gets Automotive Qualification – EE Times The non-volatile AEON memory technology has been qualified for automotive use according to the AEC-Q100 standard. The technology could compete with certain applications where hitherto EEPROMs and Flash memory has been used. Read more. Non-Volatile
