What are some of the considerations and assumptions used to develop application circuit models?
To minimize simulation time, certain parasitic elements (resistances, capacitances, inductances) have been omitted from the device models. A simulation may create voltage and/or current spikes or other waveform anomalies that would not occur, or may fail to predict voltage and/or current spikes that would occur in a physical realization of the circuit. Return to FAQ Question list.
