What are the basic design specifications of the chip?
Based on smart pixel architectures developed in the early 1990s, the proposed chip monolithically integrates optical sensors with CMOS based logic circuits. In particular, the chip described here integrates a photoreceiver with a Reduced Instruction Set Computer (RISC) to create a generically programmable smart pixel. By tiling these pixels across a two-dimensional array, it is possible to make a programmable smart pixel array that is suitable for processing optical page-oriented data streams. Figure 2 08D0C9EA79F9BACE118C8200AA004BA90B02000000080000000D0000005F00520065006600310031003100370032003600370033000000 shows a block diagram that highlights the major components of the proposed chip. As indicated in the figure, the chip architecture includes 1 (or more) processing elements (PE) and an instruction fetch unit (IFU). The IFU serves as an interface between the PE array and the off-chip shared memory. In addition to providing an instruction buffer for the PE array, the IFU is capable