What are the timing requirements for the mode select inputs?
Figure 1. Mode-select input timing The 750GX mode selects have several timing constraints (refer to Figure 1 and the Input Timing section of the appropriate datasheet): 1. The mode selects must be continuously valid for the eight SYSCLK cycles preceding the clock on which HRESET# is sampled high (inactive) (see Timing 10C, Figure 1) so that the internal state machines can be properly initialized. 2. The mode selects must be deasserted within three SYSCLK cycles of the deassertion of HRESET# (Timing 11C max, Figure 1) so that the bus state machine does not misinterpret these signals as active bus signals. 3. The mode selects do not have to be held in the valid state (as a strapping pin) for any clock cycles following the deassertion of HRESET# (Timing 11C min, Figure 1). In the example of the MODE_INPUT# in Figure 1, the designer selects the function that is activated by holding the input low leaving hreset. In this case, MODE_INPUT# must be held asserted for at least the eight clock cy
