What is the relationship between the CPU, chipset, bus, and memory?
A contemporary CPU does not talk directly to the main system DRAM memory, but through one or more intermediaries. One reason for the complexity is that as CPU speeds increase they are waiting longer and longer periods for the slow DRAM memory to respond. A second reason is that fast memory (the kind that fast CPUs would prefer) is very expensive compared to DRAM. Typically the CPU will talk first to L1 cache that is a small amount of very specialized static RAM memory running at the same speed as the processor. The L1 cache memory typically talks to a larger amount of specialized L2 cache static memory residing on or near the CPU, and under the direction of an onboard L2 cache controller. L2 cache is physically located on the chip in the new Celerons of Intel, or next to the CPU on what is called the backside bus for the slot 1 and slot 2 Intel cards, or on a bit of nearby motherboard real estate in older Pentium and 486 systems. The L2 cache then talks with the main DRAM memory throug
