When a Flash timing excess was detected by the timing limit excess flag DQ5 (DQ6 = “toggle” and DQ5 = “1”), does the RDYINT bit become “1”?
• Answer :When a Flash timing excess is detected by the timing limit excess flag DQ5 (DQ6 = “toggle” and DQ5 = “1”), neither the RDYINT bit nor RDY bit becomes “1.” Therefore, the Flash error status (timing limit excess) cannot be detected by the Flash memory control status register (FMCS). It can be detected only by the Flash hardware sequence flag.
