Why does the Ethernet interface stop working when code is uploaded to the user CPLD?
The user CPLD is coupled into the CPU IO XWAIT signal (on CPLD pin 25) which allows I/O cycles to be extended by slow peripherals. The XWAIT is only used by the CPU within the first external chip select region (CS0). The inverted I/O wait request from the Ethernet controller is also brought to the CPLD (pin 20). The designer must ensure the relevant logic is used to combine the nWAIT input and any internal I/O wait requirement to generate a correct XWAIT output. This is also covered in the EB675001DIP user guide and is included in all the supplied templates.