For the Enhanced Mini-ACE™ built-in self-test, if the flag supplying the results of the comprehensive protocol self-test and RAM self-test is faulted in the “PASS” state, how is that detected?
A. While the Enhanced Mini-ACE™’s protocol or RAM self-test is being performed, the host may access the BIT Test Status Register (register address 1Ch). However, the host may not access any of the other registers; if it does, the self-test will be aborted. While the test is being performed, the “PROTOCOL SELF-TEST PASSED” bit (bit 12) and “RAM BUILT-IN SELF-TEST PASSED” bit (bit 5) will normally be logic “0”. If you poll this register while the self-test is being performed and the “PASSED” bit for the test that’s being performed returns a value of logic “1”, this indicates that the bit is stuck high. Also, after the self-test completes, you may poll the final value of the self-test ROM address register and self-test data register. These are both test registers, which are made accessible by setting 64-WORD REGISTER SPACE, bit 2 of Configuration Register #6, to a value of logic “1”. Assuming that the test has run to successful completion, the expected values of these two registers are kn
Related Questions
- For the Enhanced Mini-ACE™ built-in self-test, if the flag supplying the results of the comprehensive protocol self-test and RAM self-test is faulted in the "PASS" state, how is that detected?
- How long does the Enhanced Mini-ACE™’s RAM self-test take to perform?
- What exactly is done in the Enhanced Mini-ACE™ RAM self-test?
