How much faster will programs execute using the SCTL?
Using a traditional While Loop in your FPGA VI takes an absolute minimum of 3 ticks to execute each iteration. This is because of the enable chain used in the compiled FPGA VI. An explanation of the enable chain is beyond the scope of this document, but is used to ensure dataflow when the FPGA VI is compiled into a bitfile. Additionally, each function inside the While Loop will require at least one tick to execute, although functions will execute in parallel if there is no data dependency. With the SCTL, all functions inside the loop must execute within a single tick. The performance benefits of using a SCTL in your FPGA VI will vary depending on what is in the loop. If your code can compile successfully inside a SCTL instead of a normal loop, you will notice a marked performance improvement.
