Is There a printf() Like Function in VHDL?
The easiest way to implement a similar functionality in VHDL is by using the image attribute of VHDL-93. See Section 4.2.21 for further information. For a package providing C-style formatted printing see Section 4.10. 4.2.30 How to Code a Clock Divider The following example will divide the clock frequency of the “ClkIn” signal by “Modulus” and output it on “ClkOut”. It produces a symmetric output waveform if “Modulus” is even, otherwise it stays low for one input clock longer than it stays high (for a VHDL model with 50%-duty-cycle for odd divisor rates see http://www.e-insite.net/ednmag/archi…7/17di_01.htm; the architecture of some “unusual” clock dividers is shown in http://www.xilinx.com/xcell/xl33/xl33_30.pdf). entity ClockDivider is generic(Modulus: in Positive range 2 to Integer’High); port(ClkIn: in bit; Reset: in bit; ClkOut: out bit); end ClockDivider; architecture Behavior of ClockDivider is begin process (ClkIn, Reset) variable Count: Natural range 0 to Modulus-1; begin if
