minimum module name length in 6.3i?
75617: 04/11/10: Re: VirtexII-Pro MGT: 8/10 coding bypass problems 76989: 04/12/18: Re: Digital clock synthesis 77019: 04/12/20: Re: PCI doubt 77144: 04/12/25: Re: Synchronous design and power consumption 77146: 04/12/25: Re: Synchronous design and power consumption 77150: 04/12/25: Re: Synchronous design and power consumption 77262: 05/01/02: Re: Free IP-Core for FPGA Config from MMC-Cards 77471: 05/01/07: Re: San Jose job offer – need advice 78480: 05/02/01: Pericom PI6C2404 equivalent 79894: 05/02/25: dealing with NGO files 79914: 05/02/25: Re: dealing with NGO files 81130: 05/03/18: Re: Performance evaluation of Distributed Arithmetic architectures for FIR filters 86794: 05/07/06: Spartan3 pci above 33MHz 93990: 06/01/04: Re: FPGA DVI output with CH7301 94052: 06/01/05: Re: FPGA DVI output with CH7301 94182: 06/01/07: Re: CRC error correction 94188: 06/01/07: Re: CRC error correction 98184: 06/03/06: Hitech Global 98406: 06/03/09: Virtex-4 DCM CLKFX jitter 98459: 06/03/10: Re: for