Possible CRC error on XC3S400 – now what?
128833: 08/02/07: Re: Prom alternatives for xilinx 129266: 08/02/19: Re: Virtex 4 package layout 129508: 08/02/26: Re: Interview questions 129650: 08/03/01: Re: FPGA’s be afraid, very afraid, of my wife! 129777: 08/03/05: Re: Is there any way to disable JTAG for Sptantan3AN 129832: 08/03/06: Re: I could run my program at DDR Sdram. 129858: 08/03/07: Re: Spartan-3E + SPI EEPROM 129874: 08/03/07: Re: Spartan-3E + SPI EEPROM 129875: 08/03/07: Re: SiliconBlue enters the FPGA fray 129916: 08/03/10: Re: its regarding to the Max Frequency in xilinx FPGA 130077: 08/03/14: Re: Design entries for FSM 130160: 08/03/17: Re: Xilinx Tristate Registration 130223: 08/03/18: Re: Xilinx Tristate Registration 130392: 08/03/21: Re: verilog question, break while loop to avoid combinational 131092: 08/04/10: Re: Specifying strict setup constraint in ISE 131185: 08/04/14: Re: “Multi-source in Unit” Verilog synthesis woes 131442: 08/04/21: Re: Xilinx DDR2 Interface 131654: 08/04/28: Re: the order in which som