What are the clock speed requirements for the DPLL?
A. The SCC always uses its internal baud rate generator (BRG) as an input clock to “seed” the DPLL. The DPLL needs to oversample the received data bit stream in order to extract clocking information. This means that the DPLL’s input clock needs to be running at a multiple of the actual rate of the received data bit stream. If the received data is NRZI-encoded, the DPLL input clock must run at 32 times the received data rate. The clock_source variable in the channel configuration structure must be set for X32 clock mode. If the received data is FM-encoded, the DPLL input clock must run at 16 times the received data rate. The clock_source variable must be set for X16 clock mode.
