What are the input thresholds for reset?
High to low is about 1.5V, and low to high is about 2.0V. It requires the RC reset circuit to be placed close to the reset pin. 17. I can’t use the UART reliably for serial communications. After hooking up an oscilloscope to the CLKOUT pin, I observed that at 19.6608MHz the clock is extremely unstable (more so than at our usual 16.384 MHz). Since the system clock is the time base to the UART, it may be that the unstable clock source is causing the system to have an unreliable baud rate. Answer: If the 19.6608MHz clock is extremely unstable, we must fix this problem before doing further testing. If the jitter is offset more than 5%, the PLL is not stable. You can check this by using a digital scope to measure the length of the clock period. If it is offset more than +/- 3 nSec, then the PLL is unstable.
