What are the layout design rules I should use for my technology?
Information regarding design rules for each of the fabrication technologies supported by MOSIS is available on their website here. MOSIS supports 3 separate flavors of design rules; depending on your selection of fabrication technology and your choice for lambda (half the minimum feature size), you will want to use one of the 3 design rule sets: • SCMOS – Scalable CMOS design rules, originally developed for processes with feature sizes greater than 1.0 m. • SCMOS_SUBM – Sub-Micron Scalable CMOS design rules, enhanced from SCMOS to better fit processes with feature sizes below 1.0 m. • SCMOS_DEEP – Deep-sub-micron Scalable CMOS design rules, enhanced from SCMOS_SUBM to better fit processes with feature sizes at and below 0.25 m. Links to design rules for some tested technologies are available under the Technology Setup page here. After clicking the appropriate link, you will be brought to a page containing the Layer Map specific to the chosen technology. The Layer Map contains all the p
