What is the maximum response time to assertion of INT?
The response time of the 750 is indeterminate because of the many factors involved. Assume that the maximum time from the assertion of the INT# signal until the first instruction of the interrupt handler is fetched is needed. First, the exception has to be recognized, which usually takes one or two bus clocks, depending on the timing. At that point, the interrupt pin could be disabled for some reason; the software is flushing a cache or another interrupt service routine is running. Once the interrupt is recognized, the next instruction in program order has to complete. This could take awhile, if it is a sync, isync, or tlbisync, or if certain bus transactions are in progress. Another, higher priority, exception could occur and pre-empt the INT# handler. Once the decision is made to fetch the ISR, various bus transactions – other masters, snoop retries, etc., can operate to further delay things. So, it is very difficult to predict the latency of the INT# pin. For more information, see t
