Whats the module interface ?
The interface for your hardware module is defined by your C code. By default every generated module has Clock and Reset inputs. In addition the generated module has ReturnValue and Ready outputs to indicate the return value of the function and to signal when the operation is completed. For any other integer parameter the synthesis will generate an input parameter. For any pointer in your function parameter list, the synthesis will generate a block-ram port. You will be able to connect each array parameter to an external block-ram port. The memory ports have the standard input, output, address and write-enable signals. This chart below explains the relationship between the argument list and the generated module. Notice how the two array parameters became two memory ports. In addition to the standard memory port entries there is a base parameter. This parameter is the offset of the array inside the block-ram.
