Why doesn the PLL make my reference input and the clock outputs line up?
The PLL will make the reference and input clock edges align at the input of the phase-frequency detector (PFD). The path from the input clock to the output is different than the path from the input clock to the PFD. Therefore, the propagation delay difference between these two paths is not compensated for by the PFD. As such, the AD9510/11 are not “zero-delay” clock parts.
