Why should an ASIC designer write code that can target an FPGA?
With the density of the Xilinx Virtex-E devices expected to exceed 3 million gates in 2000, FPGAs are becoming a more attractive alternative for designs that were typically targeted at ASICs. With more and more IP available from both internal and external sources, companies now have the option to use FPGAs for large, performance-driven designs. IP can be used in a modular design environment in the same way that cell based designs are done today. When ASIC designers code their HDL to be FPGA “friendly,” they gain more options in the ever-increasing pressure to beat the competition to market. While a particular coding technique will optimize the use of logic resources and the performance in an FPGA, it can also do the same for an ASIC design. Many of the guidelines in the Xilinx reuse manual for programmable logic are simply good design practices and will enhance IP reuse and performance. Some of the concepts that target FPGAs include documentation, implementation, verification and codin
